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MC14551B Quad 2-Channel Analog Multiplexer/Demultiplexer
The MC14551B is a digitally-controlled analog switch. This device implements a 4PDT solid state switch with low ON impedance and very low OFF Leakage current. Control of analog signals up to the complete supply voltage range can be achieved.
Features
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16 PDIP-16 P SUFFIX CASE 648 1 16 SOIC-16 D SUFFIX CASE 751B 1 1 14551BG AWLYWW MC14551BCP AWLYYWWG
* Triple Diode Protection on All Control Inputs * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Analog Voltage Range (VDD - VEE) = 3.0 to 18 V * * * * *
Note: VEE must be v VSS Linearized Transfer Characteristics Low Noise -- 12 nVCycle, f 1.0 kHz typical For Low RON, Use The HC4051, HC4052, or HC4053 High-Speed CMOS Devices Switch Function is Break Before Make Pb-Free Packages are Available*
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MAXIMUM RATINGS
Parameter Symbol VDD Value Unit V V DC Supply Voltage Range (Referenced to VEE, VSS VEE) - 0.5 to + 18.0 - 0.5 to VDD + 0.5 10 25 500 - 55 to + 125 - 65 to + 150 260 Input or Output Voltage (DC or Transient) (Referenced to VSS for Control Input and VEE for Switch I/O) Input Current (DC or Transient), per Control Pin Switch Through Current Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Vin, Vout 1 Iin Isw PD TA Tstg TL mA mA mW _C _C _C A WL, L YY, Y WW, W G Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD for control inputs and VEE (Vin or Vout) VDD for Switch I/O. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE or VDD). Unused outputs must be left open. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
16 SOEIAJ-16 F SUFFIX CASE 966 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package MC14551B ALYWG
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
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June, 2006 - Rev. 6
Publication Order Number: MC14551B/D
MC14551B
PIN ASSIGNMENT
W1 X0 X1 X Y Y0 VEE VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD W0 W Z Z1 Z0 Y1 CONTROL SWITCHES IN/OUT 9 15 1 2 3 6 10 11 12 CONTROL W W0 W1 X0 X1 Y0 Y1 Z0 Z1 X
14 4 COMMONS OUT/IN
Y Z
5 13
VDD = Pin 16 VSS = Pin 8 VEE = Pin 7
Control 0 1
ON W0 X0 Y0 Z0 W1 X1 Y1 Z1
NOTE: Control Input referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be v VSS.
ORDERING INFORMATION
Device MC14551BCP MC14551BCPG MC14551BD MC14551BDG MC14551BDR2 MC14551BDR2G MC14551BF MC14551BFG Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOEIAJ-16 SOEIAJ-16 (Pb-Free) 50 Units / Rail 2500 / Tape & Reel 48 Units / Rail 25 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC14551B
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ELECTRICAL CHARACTERISTICS
- 55_C 25_C 125_C Characteristic VDD Test Conditions Symbol Min Max Min Typ (Note 2) Max Min Max Unit SUPPLY REQUIREMENTS (Voltages Referenced to VEE) Power Supply Voltage Range Quiescent Current Per Package - 5.0 10 15 VDD - 3.0 VSS VEE Control Inputs: Vin = VSS or VDD, Switch I/O: VEE v VI/O v VDD, and DVswitch v 500 mV (Note 3 ) TA = 25_C only (The channel component, (Vin - Vout)/Ron, is not included.) VDD IDD 3.0 - - - 18 5.0 10 20 3.0 - - - - 0.005 0.010 0.015 18 5.0 10 20 3.0 - - - 18 150 300 600 V mA Total Supply Current (Dynamic Plus Quiescent, Per Package) 5.0 10 15 ID(AV) Typical (0.07 mA/kHz) f + IDD (0.20 mA/kHz) f + IDD (0.36 mA/kHz) f + IDD mA CONTROL INPUT (Voltages Referenced to VSS) Low-Level Input Voltage 5.0 10 15 5.0 10 15 15 - Ron = per spec, Ioff = per spec Ron = per spec, Ioff = per spec Vin = 0 or VDD VIL - - - 3.5 7.0 11 - - 1.5 3.0 4.0 - - - 0.1 - - - - 3.5 7.0 11 - - 2.25 4.50 6.75 2.75 5.50 8.25 0.00001 5.0 1.5 3.0 4.0 - - - 0.1 7.5 - - - 3.5 7.0 11 - - 1.5 3.0 4.0 - - - 1.0 - V High-Level Input Voltage VIH V Input Leakage Current Input Capacitance Iin Cin mA pF SWITCHES IN/OUT AND COMMONS OUT/IN -- W, X, Y, Z (Voltages Referenced to VEE) Recommended Peak-to- Peak Voltage Into or Out of the Switch Recommended Static or Dynamic Voltage Across the Switch (Note 3) (Figure 3) Output Offset Voltage ON Resistance - Channel On or Off VI/O 0 VDD 0 - VDD 0 VDD Vp-p - Channel On DVswitch 0 600 0 - 600 0 300 mV - 5.0 10 15 Vin = 0 V, No Load DVswitch v 500 mV (Note 3), Vin = VIL or VIH (Control), and Vin = 0 to VDD (Switch) VOO Ron - - - - 800 400 220 - - - - 10 250 120 80 - 1050 500 280 - - - - - 1200 520 300 mV W DON Resistance Between Any Two Channels in the Same Package Off-Channel Leakage Current (Figure 8) 5.0 10 15 15 Vin = VIL or VIH (Control) Channel to Channel or Any One Channel Switch Off DRon - - - - 70 50 45 100 - - - - 25 10 10 0.05 70 50 45 100 - - - - 135 95 65 1000 W Ioff nA Capacitance, Switch I/O Capacitance, Common O/I Capacitance, Feedthrough (Channel Off) - - - - Pins Not Adjacent Pins Adjacent CI/O CO/I CI/O - - - - - - - - - - - - 10 17 0.15 0.47 - - - - - - - - - - - - pF pF pF 2. Data labeled "Typ" is not to be used for design purposes, but is intended as an indication of the IC's potential performance. 3. For voltage drops across the switch (DVswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.)
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MC14551B
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ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C, VEE v VSS)
Characteristic Symbol VDD - VEE Vdc Min - Typ (Note 4 ) Max Unit ns Propagation Delay Times Switch Input to Switch Output (RL = 10 kW) tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 11 ns tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns Control Input to Output (RL = 10 kW) VEE = VSS (Figure 4) tPLH, tPHL 5.0 10 15 tPLH, tPHL 5.0 10 15 - BW 10 10 - - - 350 140 100 0.07 17 875 350 250 - - % MHz 35 15 12 90 40 30 ns Second Harmonic Distortion RL = 10 kW, f = 1 kHz, Vin = 5 Vp-p Bandwidth (Figure 5) RL = 1 kW, Vin = 1/2 (VDD - VEE) p-p, 20 Log (Vout / Vin) = - 3 dB, CL = 50 pF Off Channel Feedthrough Attenuation, Figure 5 RL = 1 kW, Vin = 1/2 (VDD - VEE) p-p, fin = 55 MHz Channel Separation (Figure 6) RL = 1 kW, Vin = 1/2 (VDD - VEE) p-p, fin = 3 MHz Crosstalk, Control Input to Common O/I, Figure 7 R1 = 1 kW, RL = 10 kW, Control tr = tf = 20 ns - - - 10 10 10 - - - - 50 - 50 75 - - - dB dB mV 4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
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MC14551B
VDD IN/OUT
VDD
VDD OUT/IN
VEE
VDD LEVEL CONVERTED CONTROL
IN/OUT CONTROL VEE
OUT/IN
Figure 1. Switch Circuit Schematic
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VDD
CONTROL 9
LEVEL CONVERTER
CONTROL
8 W0 15 W1 1 X0 2 X1 3 Y0 6 Y1 10 Z0 11 Z1 12
VSS
7
VEE 14 W
4X
5Y
13 Z
Figure 2. MC14551B Functional Diagram
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MC14551B
TEST CIRCUITS
CONTROL SECTION OF IC ON SWITCH PULSE GENERATOR V SOURCE VDD VEE VEE VDD LOAD
CONTROL RL CL
Vout
Figure 3. DV Across Switch
Figure 4. Propagation Delay Times, Control to Output
Control input used to turn ON or OFF the switch under test. RL ON CONTROL RL Vout CL = 50 pF CONTROL OFF RL Vin VDD - VEE 2 VDD - VEE 2 Vin Vout CL = 50 pF
Figure 5. Bandwidth and Off-Channel Feedthrough Attenuation
Figure 6. Channel Separation (Adjacent Channels Used for Setup)
OFF CHANNEL UNDER TEST VDD CONTROL SECTION OF IC VEE OTHER CHANNEL(S) VEE VDD VEE VDD
CONTROL RL R1
Vout CL = 50 pF
Figure 7. Crosstalk, Control Input to Common O/I
Figure 8. Off Channel Leakage
VDD KEITHLEY 160 DIGITAL MULTIMETER 10 k VDD VEE = VSS 1 kW RANGE X/Y PLOTTER
Figure 9. Channel Resistance (RON) Test Circuit
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MC14551B
TYPICAL RESISTANCE CHARACTERISTICS
350 RON, ON" RESISTANCE (OHMS) RON, ON" RESISTANCE (OHMS) 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 2.0 4.0 6.0 TA = 125C 25C - 55C 8.0 10 350 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 2.0 4.0 TA = 125C 25C - 55C
6.0
8.0
10
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 10. VDD @ 7.5 V, VEE @ - 7.5 V
Figure 11. VDD @ 5.0 V, VEE @ - 5.0 V
700 RON, ON" RESISTANCE (OHMS) RON, ON" RESISTANCE (OHMS) 600 500 400 300 200 100 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 2.0 TA = 125C 25C - 55C 4.0 6.0 8.0 10
350 300 250 200 150 100 50
TA = 25C VDD = 2.5 V
5.0 V 7.5 V
0 - 10 - 8.0 - 6.0 - 4.0 - 2.0
0
2.0
4.0
6.0
8.0
10
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD @ 2.5 V, VEE @ - 2.5 V
Figure 13. Comparison at 25_C, VDD @ - VEE
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MC14551B
APPLICATIONS INFORMATION Figure A illustrates use of the on-chip level converter detailed in Figure 2. The 0-to-5.0 V Digital Control signal is used to directly control a 9 Vp-p analog signal. The digital control logic levels are determined by VDD and VSS. The VDD voltage is the logic high voltage; the VSS voltage is logic low. For the example, VDD = + 5.0 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by VDD and VEE. The VDD voltage determines the maximum recommended peak above VSS. The VEE voltage determines the maximum swing below VSS. For the example, VDD - VSS = 5.0 V maximum swing above VSS; VSS - VEE = 5.0 V maximum swing below VSS. The example shows a 4.5 V
+5 V VDD +5 V 9 Vp-p ANALOG SIGNAL SWITCH I/O VSS VEE
signal which allows a 1/2 V margin at each peak. If voltage transients above VDD and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between VDD and VEE is 18 V. Most parameters are specified up to 15 V which is the recommended maximum difference between VDD and VEE. Balanced supplies are not required. However, VSS must be greater than or equal to VEE. For example, VDD = + 10 V, VSS = + 5.0 V, and VEE = - 3.0 V is acceptable. See the table below.
-5 V
+ 4.5 V 9 Vp-p ANALOG SIGNAL
COMMON O/I MC14551B
GND
EXTERNAL CMOS DIGITAL CIRCUITRY
0-TO-5 V DIGITAL CONTROL SIGNAL
CONTROL
- 4.5 V
Figure A. Application Example
VDD
VDD
Dx SWITCH I/O Dx COMMON O/I
Dx
Dx
VEE
VEE
Figure B. External Schottky or Germanium Clipping Diodes
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POSSIBLE SUPPLY CONNECTIONS
VDD In Volts +8 +5 +5 +5 VSS In Volts 0 0 0 0 VEE In Volts -8 Control Inputs Logic High/Logic Low In Volts + 8/0 + 5/0 + 5/0 + 5/0 Maximum Analog Signal Range In Volts + 8 to - 8 = 16 Vp-p - 12 0 + 5 to - 12 = 17 Vp-p + 5 to 0 = 5 Vp-p -5 -5 + 5 to - 5 = 10 Vp-p + 10 + 10/ + 5 + 10 to - 5 = 15 Vp-p
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MC14551B
PACKAGE DIMENSIONS
PDIP-16 CASE 648-08 ISSUE T
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC14551B
PACKAGE DIMENSIONS
SOEIAJ-16 CASE 966-01 ISSUE A
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC14551B/D

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